1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device that includes a cylindrical capacitor.
2. Description of the Related Art
Higher cell capacitance is often used to improve characteristics of a memory cell in a dynamic random access memory (DRAM) device. The increased cell capacitance improves read-out capacity of the memory cell and reduces soft errors. Meanwhile, as semiconductor memory devices have become more highly integrated, the unit memory cell of the semiconductor memory device has continuously decreased in area. As a result, a capacitor in the unit memory cell has also needed to continuously decrease in area.
Capacitors having a high capacitance that are formed in typically restricted areas have been studied. These studies are mainly directed to a three-dimensional structure of a storage node electrode in a capacitor for increasing an effective area of the capacitor. Currently, various storage node electrodes having a three-dimensional structure such as a trench structure, a stacked structure, a cylindrical structure, and a combination thereof, as well as other structures have been developed.
Attempting to increase the capacitance by improving the structure of the storage node electrode, however, is restricted due to a limit of a design rule, increases of error ratios caused by complicated processes, etc. As a result, most attempts are regarded skeptically with respect to the possibility of producing a capacitor having the above-mentioned structures. Therefore, a method of manufacturing a capacitor that is capable of overcoming the above-mentioned problems is in demand. In particular, to improve a capacitance of the cylindrical capacitor requires forming a storage node electrode having a greatly increased height.
However, the storage node electrode collapses due to its increased height, creating an electrical bridge between adjacent storage node electrodes.
To prevent these bridges, a method for forming a storage electrode of a cylindrical capacitor is disclosed in Korean Patent Laid Open Publication No. 2002-0073942. According to the above disclosure, an insulating interlayer on a semiconductor substrate is patterned using a photoresist pattern to form a linear pattern. A fixing layer that includes an insulation material, for example silicon nitride, is formed on the linear pattern to prevent a collapse or lean of a capacitor.
FIGS. 1 to 4 are cross-sectional views illustrating a conventional method of forming a storage electrode of a cylindrical capacitor that has a lean-preventing structure.
Referring to FIG. 1, a cylindrical storage electrode 40 is formed on a semiconductor substrate 10, which includes a lower structure having a contact plug 12 and a contact pad 22 to electrically contact the cylindrical storage electrode 40 with the contact plug 12. The semiconductor substrate 10 is divided into a cell array region and a peripheral region.
The cylindrical storage electrode 40 is formed in the cell array region to contact an upper face of the contact pad 22. A dielectric layer 60 and a plate electrode 70 are sequentially formed on the cylindrical storage electrode 40. Here, a reference numeral 30 refers to an etching stop layer pattern, and a reference numeral 50 refers to a supporting layer pattern, which is connected between the adjacent storage electrodes 40, for preventing a collapse of the storage electrodes 40.
Referring to FIG. 2, a sacrificial layer 80 is formed on the plate electrode 70. Here, the sacrificial layer 80 is positioned in the cell array region and the peripheral region. Thus, a portion of the sacrificial layer 80 in the cell array region has a height higher than that of a portion of the sacrificial layer 80 in the peripheral region.
Referring to FIG. 3, a mask layer pattern (not shown) that covers the peripheral region and exposes the cell array region is formed on the sacrificial layer 80. The sacrificial layer 80 is partially etched by a dry etching process using the mask layer pattern as an etching mask. The mask layer pattern is then removed.
Referring to FIG. 4, the etched sacrificial layer 80 is planarized to expose the plate electrode 70 in the cell array region.
To readily perform the dry etching process and the planarization process by the above-mentioned conventional method unfortunately requires the sacrificial layer 80 to have a large thickness of more than about 20,000 Å.
Also, the planarization process is expensive. As a result, the photolithography process, the dry etching process, and the planarization process of the conventional methods for forming the capacitor are complicated and costly.